The present invention relates generally to methods of forming ohmic contacts between metallization layers and device elements in semiconductor devices. More particularly, the invention relates to methods of forming contacts that include tantalum-containing barrier layers.
In the manufacture of integrated circuits, a conductive metal, such as aluminum or an aluminum alloy, is typically used to form the interconnections or "wiring" between the various semiconductor devices making up the chip. More specifically, the interconnections are electrically conductive paths between various device elements of the devices making up the integrated circuit. Each such device element must make an ohmic contact with an interconnection. In the case of MOS-based integrated circuits, device elements requiring ohmic contacts to metal interconnects include sources, drains, and gate electrodes. In addition, the well regions in which MOS devices are formed generally require ohmic contacts to metal interconnections.
Herein the process of depositing the conductive metal, along with any other corresponding steps, is termed "contact metallization" or simply "metallization". Once deposited, the conductive metal layer is called a "metallization layer".
In the fabrication of integrated circuits, after the device elements are formed on a semiconductor substrate, an insulating or dielectric "blanket" layer is deposited over the substrate, thereby covering any device elements which require electrical connection. Thereafter, to enable electrical connection to these devices, interconnect regions, called "contact vias" or simply "vias", are etched through the blanket layer and expose portions of the device elements. After a few intervening steps (discussed below), a metallization layer is deposited. To successfully form ohmic contacts, the metallization layer (or some other electrically conductive material) must extend down into and conformally fill the contact vias. Otherwise gaps may remain in the via and prevent reliable electrical contact. Thus, the process steps and conditions must be conducted under conditions which provide adequate filling of the vias.
Between the step of forming vias in the insulating blanket layer and the step of depositing a metallization layer, a diffusion barrier is formed over the top of the insulating layer. This is to prevent species from the metallization (often copper present in the aluminum metallization) from diffusing into the substrate and degrading device performance. Thus, diffusion barriers are made from materials which prevent diffusion while still allowing good electrical contact between the metallization layer and the substrate.
A conventional process for forming a contact to an MOS source will now be described with reference to FIG. 1. Beginning with a partially fabricated MOS device, a silicon substrate 20 includes a source region 22, a gate electrode 24, and a drain region 26. A field oxide region 28, located adjacent to the source region, partially covers the silicon substrate 20 and electrically isolates adjacent devices. Initially, a non-conductive blanket layer 30 comprised of a low temperature oxide/borophosphosilicate glass is conformally deposited on substrate 20. Next, a via is etched through the blanket layer 30, thereby exposing a portion of the source region 22. It should be noted that in actual processes, vias are simultaneously formed over gates, drain regions, source regions, and well regions. To simplify illustration, however, only the source region via will be shown. After the via has been formed, a titanium (Ti) layer 32 is conformally deposited over the structure. Thereafter, a titanium nitride (TiN) layer 33 is conformally deposited over Ti layer 32. Next, the MOS device is subjected to a rapid thermal anneal (RTA) step to cause some Ti from the Ti layer to diffuse into source region 22 and form a titanium silicide ohmic contact 31.
Following the RTA, a blanket layer of Tungsten (W) is deposited over the partially fabricated chip at a temperature typically about 450.degree. C. followed by an etchback process removing all the blanket W layer except a plug 34. Next, a second TiN barrier layer 36 is deposited over the tungsten filled via 34. At this point, the upper surface of the structure is relatively flat and contains no unfilled vias. On this surface, an aluminum metallization layer 38 is now deposited, overlying the second barrier layer 36. The temperature of this deposition step is conventionally about 275.degree.-300.degree. C. As explained below, at this temperature, the aluminum metallization layer is unable to conformally fill the vias. Thus, tungsten is used to conformally fill the vias and provide a relatively flat surface for metallization. Of course, this results in increased process complexity. Specifically, between the steps of forming barrier layers 33 and 36, the partially fabricated chip must be transferred to different processing equipment to form the tungsten layer. In a final step, an anti-reflective TiN layer 40 is deposited over the metallization layer 38 to facilitate subsequent photolithographic patterning of layer 38 to form lines.
In the above method, the processing temperature is maintained below about 600.degree.-650.degree. C. Beyond this temperature range, the barrier properties of TiN degrade and diffusion between the substrate 20 and the W plug 34 begin to become significant. Thus, the aluminum metallization layer is deposited at the relatively low temperature of 275.degree.-300.degree. C. As noted, this is too low to allow the aluminum metallization to conformally fill the vias. In addition, aluminum deposited at this temperature cannot form a planer upper surface, thus requiring a subsequent polishing or other planarization step.
In discussing the size of vias, often a parameter called the "minimum step coverage" determines the smallest allowable via. FIG. 2 ("prior art") provides a cross-sectional illustration of a contact produced by depositing a metallization layer in a via and will serve as an example for explaining the term minimum step coverage. In this example, the substrate 10 is covered by a non-conductive passivation layer 12, a diffusion barrier layer 16, and a metallization layer 18. As shown, the metallization layer 18 fails to completely fill the via. Instead, the metallization layer 18 covers the barrier layer 16 but leaves an empty pocket 19 within the via.
The step coverage for this example (and in general) is found by first dividing a lateral dimension .DELTA. (which is the thickness of the metallization layer within the via) by a longitudinal dimension .beta. (which is the thickness of the metallization layer outside of the via). This factor, .DELTA./.beta., is then multiplied by 100 to yield a number which is by definition the step coverage. If the step coverage for the contact is less than the predetermined minimum step coverage, then this contact is defective. That is, the contact will almost certainly fail, even if it conducts initially. This problem is now addressed by using tungsten plugs which conformally deposit in smaller vias at low temperatures.
Present manufacturing processes attain a minimum via size of perhaps 0.4 microns in the lateral direction (Please note that this number is given primarily as a reference point for the following discussion). However, there is a continuing demand for increased semiconductor device packing density. This demand can only be met by decreasing the sizes of all components in the semiconductor device. Accordingly, the size of the vias interconnecting these components has continually decreased (and will continue to do so). Thus, vias having a minimum size of less than 0.4 microns will be required in future generations of integrated circuits. Furthermore, any other improvements over the current manufacturing process, such as fewer and/or simpler processing steps, will provide the user of the improved technology a competitive advantage.
In view of the above, it is apparent that an improved process for forming ohmic contacts in integrated circuits is required. Such process should be less complex than the conventional processes employing tungsten plugs. In addition, the improved process should be able to meet the demands of next generation integrated circuits which will require smaller vias.